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MAX9160

Features: LVDS or LVTTL/LVCMOS Input SelectionLVDS Input Fail-Safe Sets Outputs High for Open,Undriven Short, or Undriven Parallel TerminationTwo Output Banks with Separate Bank EnablesIntegrated Output Series Termination for 60Ω Lines200ps (max) Output-to-Output Skew±100ps (max) Peak-to-Pea...

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SeekIC No. : 004412573 Detail

MAX9160: Features: LVDS or LVTTL/LVCMOS Input SelectionLVDS Input Fail-Safe Sets Outputs High for Open,Undriven Short, or Undriven Parallel TerminationTwo Output Banks with Separate Bank EnablesIntegrated Ou...

MAX9160 Data Sheet

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Part Number:
MAX9160
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

LVDS or LVTTL/LVCMOS Input Selection
LVDS Input Fail-Safe Sets Outputs High for Open,Undriven Short, or Undriven Parallel Termination
Two Output Banks with Separate Bank Enables
Integrated Output Series Termination for 60Ω Lines
200ps (max) Output-to-Output Skew
±100ps (max) Peak-to-Peak Added Output Jitter
42% to 58% Output Duty Cycle at 125MHz
Guaranteed 125MHz Operating Frequency
LVDS Input Is High Impedance with VCC= 0V or Open (Hot Swappable)
28-Pin Exposed- and Nonexposed-Pad TSSOP or 32-Lead QFN Packages
-40°C to +85°C Operating Temperature
3.0V to 3.6V Supply Voltage


Application

Cellular Base Stations
Servers
Add/Drop Multiplexers
Digital Cross-Connects
DSLAMs
Networking Equipment


Pinout

Connection Diagram


Specifications

VCC to GND..............................................................-0.3V to +4V
IN+, IN- to GND........................................................-0.3V to +4V
SE_IN, EN_, SEL, RSET, OUT_ to GND........-0.3V to VCC+ 0.3V
Output Short-Circuit Duration (OUT_) (Note 1)..........Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C).....1024mW
28-Pin TSSOP-EP (derate 23.8mW/°C above +70°C)..1904mW
32-Pin QFN (derate 21.2mW/°C above +70°C).........1704mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
ESD Protection
Human Body Model (IN+, IN-).......................................±16kV
Human Body Model (SE_IN)............................................±8kV
Soldering Temperature (10s)...........................................+300°C


Description

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be adjusted using an external resistor to set the bias current for an internal delay cell. The LVTTL/LVCMOS outputs feature 200ps maximum output-to-output skew and ±100ps maxi-mum added peak-to-peak jitter.The MAX9160 is designed to operate with a 3.3V sup-ply voltage over the extended temperature range of -40°C to +85°C. This MAX9160 is available in 28-pin exposed- and nonexposed-pad TSSOP and 32-lead 5mm x 5mm QFN packages.




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