MAX3634

Features: DC-Coupled Clock Phase Aligner for Burst-Mode GPON Applications13-Bit Burst Acquisition Time0.85UI High-Frequency Jitter ToleranceContinuous Clock OutputByte Rate (1/8th Data Rate) Reference Clock InputLock Detect OutputLVPECL Serial Data Input and OutputLVPECL Reset InputApplication622M...

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SeekIC No. : 004410093 Detail

MAX3634: Features: DC-Coupled Clock Phase Aligner for Burst-Mode GPON Applications13-Bit Burst Acquisition Time0.85UI High-Frequency Jitter ToleranceContinuous Clock OutputByte Rate (1/8th Data Rate) Referen...

floor Price/Ceiling Price

Part Number:
MAX3634
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

DC-Coupled Clock Phase Aligner for Burst-Mode GPON Applications
 13-Bit Burst Acquisition Time
 0.85UI High-Frequency Jitter Tolerance
Continuous Clock Output
Byte Rate (1/8th Data Rate) Reference Clock Input
Lock Detect Output
 LVPECL Serial Data Input and Output
 LVPECL Reset Input



Application

622Mbps GPON OLT Receivers
1244Mbps GPON OLT Receivers



Pinout

  Connection Diagram


Specifications

VCC, VCCI, VCCO, VCCV........................................-0.5V to +4.0V
SDI±, RST±, REFCLK±,
RATESEL, FILT, TEST.................................-0.5V to (VCC + 0.5V)
LVPECL Output Current (SDO±, SCLK±, LOCK±).............50mA
Continuous Power Dissipation (TA = +85°C)48-Lead TQFN package
(derate 27.8mW/°C above +85°C).............................1800mW
Storage Temperature Range .........................-55°C to +150°C
Operating Ambient Temperature Range ..........-40°C to +85°C
Lead Temperature (soldering, 10s) ...............................+400°C



Description

The MAX3634 burst-mode clock phase aligner (CPA) is designed specifically for 622Mbps or 1244Mbps GPON (ITU G.984) optical line terminal (OLT) receiver applications. The MAX3634 provides clock and clock-aligned resynchronized upstream data through differential LVPECL outputs. Using the OLT system clock as a reference, the MAX3634 aligns to the input data and acquires within the first 13 bits of the burst. The CPA operates with received data that is frequency locked to the OLT reference. The acquisition time, bit-error ratio, and jitter tolerance all support GPON PMD specifications. LVPECL high-speed clock and data outputs provide compatibility with FPGAs at 622Mbps and with the MAX3885 deserializer at 1244Mbps.

The MAX3634 is available in a low-profile, 7mm x 7mm, 48-lead TQFN package. The MAX3634 operates from a single +3.3V supply, over the -40°C to +85°C temperaturerange.




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