MAX3620

Features: Supports HSTL Source Terminated Lines All-Passive Design Compatible with 100Ω Differential and 50Ω Single-Ended Transmission Lines Small 3mm x 3mm PackageApplicationQDR/QDRII Memory SystemsMultiphase Clock GenerationPinoutSpecificationsMaximum DC Voltage between COMMON and IO...

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MAX3620 Picture
SeekIC No. : 004410092 Detail

MAX3620: Features: Supports HSTL Source Terminated Lines All-Passive Design Compatible with 100Ω Differential and 50Ω Single-Ended Transmission Lines Small 3mm x 3mm PackageApplicationQDR/QDRII M...

floor Price/Ceiling Price

Part Number:
MAX3620
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

 Supports HSTL Source Terminated Lines
All-Passive Design
Compatible with 100Ω Differential and 50Ω Single-Ended Transmission Lines
Small 3mm x 3mm Package



Application

QDR/QDRII Memory Systems
Multiphase Clock Generation



Pinout

  Connection Diagram


Specifications

Maximum DC Voltage between COMMON and IOs
(IN1, IN2, OUT1, OUT2).........................................................±2.0V
Operating Temperature Range ............................-45°C to +85°C
Storage Temperature Range ..............................-55°C to +150°C



Description

The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a small 3mm x 3mm package which contains two delay lines of equal length that can be driven either differentially or single-endedly.




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