Features: Supports HSTL Source Terminated Lines All-Passive Design Compatible with 100Ω Differential and 50Ω Single-Ended Transmission Lines Small 3mm x 3mm PackageApplicationQDR/QDRII Memory SystemsMultiphase Clock GenerationPinoutSpecificationsMaximum DC Voltage between COMMON and IO...
MAX3620: Features: Supports HSTL Source Terminated Lines All-Passive Design Compatible with 100Ω Differential and 50Ω Single-Ended Transmission Lines Small 3mm x 3mm PackageApplicationQDR/QDRII M...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a small 3mm x 3mm package which contains two delay lines of equal length that can be driven either differentially or single-endedly.