MAX3270EMH

Number of Switches :
Switch Configuration :
On Resistance (Max) :
Switch Voltage (Max) :
On Time (Max) :
Off Time (Max) :
Operating Supply Voltage :
Maximum Operating Temperature :
Mounting Style :
Package / Case :


Features:

Supports Both 155Mbps and 622Mbps Clock
    Recovery and Data Retiming
Fully Integrated Phase/Frequency Detector
Capable of Switching to an External Clock
Differential 100K ECL Data and Clock I/Os
Output Monitor Provides Lock Detection
No External Reference Clock Required


Application

155Mbps (STM-1/OC-3)/622Mbps (STM-4/
OC-12) SDH/SONET Transmission Systems
155Mbps/622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Cross-Connects


Pinout




Specifications

VTTL to GND..........................................................-0.5V to +8.0V
V_CC to GND...........................................................-0.5V to +8.0V
V_EE to GND............................................................-8.0V to +0.5V
SDIP, SDIN, EXC....................................................-8.0V to +0.5V
RDOP, RDON, RCOP, RCON, CRP.......................-8.0V to +0.5V
EXCS, RST, CRS.....................................................-0.5V to +8.0V
FILP, FILG, FILN.....................................................-8.0V to +0.5V

PHADJ, VR..............................................................-8.0V to +8.0V
FM .........................................................................-8.0V to +8.0V
Input Differential Voltage Level, SDIP, SDIN.......................+3.0V
Continuous Power Dissipation (T_A= +85°C)........................1.3W
Operating Temperature Range..........................-40°C to +85°C
Storage Temperature Range...........................-55°C to +150°C
Lead Temperature (soldering, 10sec)..............................+300°C

Description

The MAX3270 is a complete Clock Recovery and Data Retiming IC for 155Mbps and 622Mbps SDH/SONET and ATM applications. The MAX3270 meets Bellcore and CCITT jitter tolerance specifications ensuring error- free data recovery. Recovered clock and data are phase aligned using a fully integrated phase-locked loop (PLL). An output frequency monitor (FM) is includ-ed to detect loss of PLL acquisition or a loss of input data.

The MAX3270 has differential ECL input and output interfaces, so it is less susceptible to noise in a high- frequency environment. The fully integrated PLL includes an integrated phfrequency detector that eliminates the need for external references.