MAX2391EGI

RF Receiver W-CDMA/W-TDD/TD SCDMA Zero-IF Rcvr

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SeekIC No. : 00614618 Detail

MAX2391EGI: RF Receiver W-CDMA/W-TDD/TD SCDMA Zero-IF Rcvr

floor Price/Ceiling Price

Part Number:
MAX2391EGI
Mfg:
Maxim Integrated Products
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

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Specifications

VCC to GND .............................................-0.3V to +3.6V
All Other Pins to GND ...................-0.3V to (VCC + 0.3V)
LNA_IN +15dBm
Digital Input Current .........................................±10mA
Digital Output Open-Collector Current ...................1mA
Operating Temperature Range .........-40°C to +85°C
Junction Temperature .....................................+150°C
Storage Temperature Range.......... -65°C to +160°C
Lead Temperature (soldering, 10s)................ +300°C
28-Pin QFN ......................................................1.667W
Derates above +70°C
28-Pin QFN ..............................................20.8mW/°C



Description

The MAX2391 fully integrated direct-conversion receiver IC is designed specifically for W-CDMA applications. With the MAX2395, the MAX2391 forms a complete single-mode W-CDMA radio chipset.

The MAX2391 provides a complete antenna-to-baseband solution for the 3GPP W-CDMA FDD receiver (2110MHz to 2170MHz, 3.84Mcps), eliminating the use of an off-chip IF SAW filter, as well as external RX LO generation and synthesis.

The MAX2391 receiver ICs have over 90dB of dynamic gain control, and a receive sensitivity of -112dBm referred to LNA input. The receiver consists of an ultra-low current low-noise amplifier (LNA) with on-chip output matching and a two-step gain control. The zero-IF demodulator has a differential circuit topology for minimum LO leakage to the receiver's input. The channel selectivity is done completely in the baseband section of the receiver with an on-chip lowpass filter. The AGC section has over 50dB of gain control range. LO quadrature generation is done onchip through a divide-by-2 prescaler. The DC offset cancellation in the I/Q baseband channels is done fully on-chip using a DC servo loop. To quickly correct for large DC offset transients in minimal time, very fast settling time is obtained by optimization of the DC-offset cancellation circuit's time constant.

The MAX2391 includes a 3-wire serial bus for PLL programming and for configuring the different receiver modes. It also includes a SHDN pin for full device shutdown. The MAX2391is fabricated using an advanced high-frequency SiGe BiCMOS process. The IC operates from a single +2.7V to +3.3V supply and is housed in a small 28-pin leadless QFN-EP package (5mm * 5mm).




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