Features: Excellent Dynamic Performance 68.6dB SNR at fIN= 20MHz 90dBc SFDR at fIN= 20MHzLow-Power Operation 159mW at 3.0V (Single-Ended Clock) 181mW at 3.3V (Single-Ended Clock) 198mW at 3.3V (Differential Clock)Differential or Single-Ended ClockAccepts 20% to 80% Clock Duty CycleFully Differenti...
MAX1206: Features: Excellent Dynamic Performance 68.6dB SNR at fIN= 20MHz 90dBc SFDR at fIN= 20MHzLow-Power Operation 159mW at 3.0V (Single-Ended Clock) 181mW at 3.3V (Single-Ended Clock) 198mW at 3.3V (Diff...
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VDD to GND...........................................................-0.3V to +3.6V
OVDDto GND..........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INP, INN to GND.....-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN,
COM to GND...........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND..............-0.3V to the lower of (VDD+ 0.3V) and +3.6V
D11D0, I.C., DAV, DOR to GND................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)...........................2105.3mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
The MAX1206 is a 3.3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-and- hold (T/H) input, driving the internal quantizer. The device is optimized for low power, small size, and high dynamic performance. This ADC operates from a single 3.0V to 3.6V supply, consuming only 159mW, while delivering a typical signal-to-noise ratio (SNR) per- formance of 68.6dB at a 20MHz input frequency. The T/H-driven input stage accepts single-ended or differen- tial inputs. In addition to low operating power, it features a 0.15mW power-down mode to con- serve power during idle periods.
A flexible reference structure allows the MAX1206 to use its internal precision bandgap reference or accept an externally applied reference. A common-mode refer- ence is provided to simplify design and reduce external component count in differential analog input circuits. The MAX1206 supports both a single-ended and differ- ential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer.
The MAX1206 features parallel, CMOS-compatible out- puts. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indi- cator eliminates external components that are normally required for reliable digital interfacing. A separate power input for the digital outputs accepts a voltage from 1.7V to 3.6V for flexible interfacing with various logic levels. The MAX1206 is available in a 6mm x 6mm x 0.8mm, 40- pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40°C to +85°C)temperature range. Refer to the MAX1209 and MAX1211 (see Pin-Compatible Higher/Speed Versions table) for applications that require high dynamic performance for IF input frequencies.