Features: ·Radiation Hard CMOS-SOS Technology·Fast Access Time 60ns Typical·Single 5V Supply·Inputs Fully TTL and CMOS Compatible·-55°C to +125°C OperationPinoutSpecifications Symbol Parameter Min. Max. Unit VDDVINTATS Supply VoltageInput VoltageOperating TemperatureSt...
MA7001: Features: ·Radiation Hard CMOS-SOS Technology·Fast Access Time 60ns Typical·Single 5V Supply·Inputs Fully TTL and CMOS Compatible·-55°C to +125°C OperationPinoutSpecifications Symbol Param...
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Symbol |
Parameter |
Min. |
Max. |
Unit |
VDD VIN TA TS |
Supply Voltage Input Voltage Operating Temperature Storage Temperature |
-0.5 -0.3 -55 -65 |
7.0 VDD+0.3 125 150 |
V V °C °C |
The MA7001 512 x 9 FIFO is manufactured using Dynex Semiconductor's CMOS-SOS high performance, radiation hard, 3mm technology.
The MA7001 Dynex Semiconductor Silicon-on-Sapphire process provides significant advantages over bulk silicon substrate technologies In addition to very good total dose hardness and neutron hardness >1015n/cm2, the Dynex Semiconductor technology provides very high transient gamma and single event upset performance without compromising speed of operation The Sapphire substrate also eliminates latch-up giving greater flexibility of use in electrically severe environments.
The MA7001 implements a First-ln First-Out algorithm that reads and writes data on a first-in first-out basis. The dual-port static RAM memory is organised as 512 words of 9 bits (8 bit data and 1 bit for parity or control purposes).
MA7001 Sequential read and write accesses are achieved using a ring pointer architecture that requires no external addressing information. Data is toggled in and out of the device by using the WRITE (W) and READ (R) pins.
MA7001 Full and Empty status flags prevent data overflow and underflow. Expansion logic on the device allows for unlimited expansion capability in both word size and depth. ARETRANSMIT (RT) feature allows for reset of the read pointer to its initial position to allow retransmission of data.
The device MA7001 is designed for applications requiring asynchronous and simultaneous read/write in multiprocessing and rate buffering (sourcing and sinking data at different rates eg. interfacing fast processors and slow peripherals).