MA31753

Features: · Radiation Hard CMOS SOS Technology·Four Independant DMA Channels·MIL-STD-1750A or B Operation in an MA31750 System·Capable of Processor Independant Table Driven Operation·Memory to Memory, I/O to Memory, Memory to I/O and I/O to I/O Transfers Supported·Masking of Individual Channel DMA...

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MA31753 Picture
SeekIC No. : 004407680 Detail

MA31753: Features: · Radiation Hard CMOS SOS Technology·Four Independant DMA Channels·MIL-STD-1750A or B Operation in an MA31750 System·Capable of Processor Independant Table Driven Operation·Memory to Memor...

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Part Number:
MA31753
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

· Radiation Hard CMOS SOS Technology
·Four Independant DMA Channels
·MIL-STD-1750A or B Operation in an MA31750 System
·Capable of Processor Independant Table Driven Operation
·Memory to Memory, I/O to Memory, Memory to I/O and I/O to I/O Transfers Supported
·Masking of Individual Channel DMA Requests
·Simple MA31750 Bus Interface
·Single Word, Double Word or Multi-Word Transfers for each of the DMA Channels
·Cascade Interface Allows for Channel Expansion
·Programmable Channel Priority
·Parity Checking Available





Pinout






Description

The MA31753 Direct Memory Access Controller (DMAC) is a peripheral interface circuit design primarily for use with the MA31750 microprocessor. Each DMAC provides up to four independant, prioritised channels each of which can perform DMA transfers between memory and/or I/O devices using the MA31750 bus. Each channel has its own programmable internal priority and can be masked under program control. Further, individual channels have their own associated status and control words enabling an individual channel to be reprogrammed without disturbing transfers which may be taking place on other channels. Three basic transfer modes are available:
Direct Memory to I/O peripheral transfers,
Direct I/O to Memory transfers,
Memory to Memory transfers,
I/O to I/O transfers.

The MA31753 interfaces directly to the MA31750 bus, directly supporting on chip parity generation and supporting
expanded memory via an MA31751 MMU with either 1 MWord (1750A mode) or 16MWords (1750B mode) of logical memory.

The MA31753 uses System memory to hold address and count information for each transfer. Once this information has been prepared by the processor the DMAC can conduct a number of transfers without further processor intervention.






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