Features: ` SUPPLY VOLTAGE: 2.7 to 3.3V
` ACCESS TIMES: 70ns
` LOW STANDBY CURRENT: 100µA
` DEEP POWER-DOWN CURRENT: 10µA
` BYTE CONTROL: UB/LB
` PROGRAMMABLE PARTIAL ARRAY
` COMPATIBLE WITH STANDARD LPSRAM
` TRI-STATE COMMON I/O
` 8 WORD PAGE ACCESS CAPABILITY: 18ns
` WIDE OPERATING TEMPERATURE
` TA = 30 to +85°C
` POWER-DOWN MODES
` Deep Power-Down
` 4 Mbit Partial Array Refresh
`8 Mbit Partial Array Refresh
` 16 Mbit Partial Array Refresh
Specifications
| Symbol |
Parameter |
Min |
Max |
Unit |
| IO |
Output Current |
50 |
50 |
mA |
| TA |
Ambient Operating Temperature |
30 |
85 |
|
| TSTG |
Storage Temperature |
55 |
125 |
|
| VCC |
Core Supply Voltage |
0.5 |
3.6 |
V |
| VIO |
Input or Output Voltage |
0.5 |
3.6 |
V |
DescriptionThe M69AW048B is a 32 Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range.
M69AW048B is a member of STMicroelectronics PSRAM memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area.
However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface.
The internal control logic of the M69AW048B handles the periodic refresh cycle, automatically, and without user involvement.
Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB).
The M69AW048B can be put into standby mode using Chip Enable (E1) or in Power-Down mode by using Chip Enable (E2).
The device features various kinds of Power-Down modes for power saving as a user configurable option:
·The Partial Array Refresh (PAR) performs a limited refresh of the part of the PSRAM array (4 Mbits, 8 Mbits, 16Mbits) that contains essential data.
·Deep Power-Down mode: this mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the powerdown should be less than the maximum period for refresh.
M69AW048B Data Sheet
