M69AW024B

· SUPPLY VOLTAGE: 2.7 to 3.3V
· ACCESS TIME: 60ns, 70ns
· LOW STANDBY CURRENT: 70µA
· DEEP POWER DOWN CURRENT: 10µA
· LOW VCC DATA RETENTION: 2.3V
· COMPATIBLE WITH STANDARD LPSRAM

The M69AW024B is a 16 Mbit (16,777,216 bit) CMOS memory, organized as 1,048,576 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range.

M69AW024B is a member of STMicroelectronics PSRAM memory family, based on the one-transistor per-cell architecture. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area.

However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface.  The internal control logic of the M69AW024B handles the periodic refresh cycle, automatically, and without user involvement.

Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB).

The M69AW024B can be put into standby mode using Chip Enable (E1) or in deep power down mode by using Chip Enable (E2).

Power-Down mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory.