M68AR512D

Features:

SUPPLY VOLTAGE: 1.65 to 1.95V
512K x 16 bits SRAM with OUTPUT ENABLE
EQUAL CYCLE and ACCESS TIMES: 70ns
SINGLE BYTE READ/WRITE
LOW STANDBY CURRENT
LOW V_CC  DATA RETENTION: 1.0V
TRI-STATE COMMON I/O
AUTOMATIC POWER DOWN
DUAL CHIP ENABLE for EASY DEPTH  EXPANSION


Specifications

Symbol	Parameter	Value	Unit
IO(1)	Output Current	20	mA
TA	Ambient Operating Temperature	-55 to 12
TSTG	Storage Temperature	-65 to 150
VCC	Supply Voltage	-0.5 to 2.5	V
VIO(2)	Input or Output Voltage	-0.5 to VCC +0.5	V
PD	Power Dissipation	1	W

Description

The M68AR512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation re-quiring no external clocks or timing strobes, with equal address access and cycle times. It requires ±150mV) supply. This device has a a single 1.8V (Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an auto-matic power-down feature, reducing the power consumption by over 99%.

The M68AR512D is available in TFBGA48 (6x7mm and 8x10mm, 6x8 active ball array, 0.75 mm ball pitch) package. See the Ordering Informa-tion Scheme (Table 12) for details.