M67140

Features:

Fast access time
  35 ns to 55 ns
  30 ns preliminary for commercial only
67130L/67140L low power
  67130V/67140V very low power
Expandable data bus to 16 bits or more using master/slave devices when using more than one device.
On chip arbitration logic
BUSY output flag on master
BUSY input flag on slave
INT flag for port to port communication
Fully asynchronous operation from either port
Battery backup operation :   2 V data retention
TTL compatible
Single 5V ± 10 % Power Supply (1)
  3.3 V versions are also available. Please consult sales.


Pinout




Specifications

Supply voltage (VCCGND) : . . . . . . . . . . . . . . . . . . 0.3 V to 7.0 V
Input or output voltage applied : . . . . . . . . . . . . . . . (GND 0.3 V) to (VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . 65 to + 150
* Notice
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.

OPERATING RANGE	OPERATING SUPPLY VOLTAGE	OPERATING TEMPERATURE
Military	Vcc = 5 V ± 10 %	55 to + 125
Automotive	Vcc = 5 V ± 10 %	40 to + 125
Industrial	Vcc = 5 V ± 10 %	40 to + 85
Commercial	Vcc = 5 V ± 10 %	0 to + 70

Description

The M 67130/67140 are very low power CMOS dual port static RAMs organized as 1024 * 8. They are designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bits or more width systems. The TEMIC MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic.

Master and slave devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the onchip circuitry of each port in order to enter a very low stand by power mode.

Using an array of eight transistors (8T) memory cell and fabricated with the state of the art 1.0 mm lithography named SCMOS, the M67130/140 combine an extremely low standby supply current (typ = 1.0 A) with a fast access time at 35 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 W.

For military/space applications that demand superior levels of performance and reliability the M 67130/140 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.