M67025

The M67025E has two ports with separate control, address and I/O pins that permit independent read/write access to any memory location. M67025E has an automatic power-down feature controlled by CS. CS controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not selected (CS high). When a port is selected access to the full memory array is permitted. Each port has its own Output Enable control (OE). In read mode, the port's OE turns the Output drivers on when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1.

The M67025E interrupt flag (INT) allows communication between ports or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is set when the right port writes to memory location 1FFE (HEX). The left port clears the interrupt by reading address location 1FFE. Similarly, the right port interrupt flag (INTR) is set when the left port writes to memory location 1FFF (HEX), and the right port must read memory location 1FFF in order to clear the interrupt flag (INTR). The 16-bit message at 1FFE or 1FFF is userdefined. If the interrupt function is not used, address locations 1FFE and 1FFF are not reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt function.