M66850J

• Memory configuration 64words x 9bits (M66850J/FP) 256words x 9bits (M66851J/FP) 512words x 9bits (M66852J/FP) 1024words x 9bits (M66853J/FP)
• Write and Read Clocks can be independent
• Advanced CMOS technology
• Programmable Almost-Empty and Almost-Full flags
• High-speed : 25ns cycle time
• Package Available : 32-pin Pastic Leaded Chip Carrier(PLCC) 32-pin Low profile Quad Flat Package(LQFP)

M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology.

These FIFOs are applicable for a data buffer as networks and communications.

The write operation of M66850/851/852/853 is controlled by a write clock pin(WCLK) and two write enable pins(WEN1WEN2 ).

Data present at the data input pins(D0-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writing.

The read operation is controlled by a read clock pin(RCLK) and two read enable pins(REN1,REN2).

Data is read from the Synchronous FIFO on every rising read clock edge when the device is enabled for reading. An output enable pin(OE) controls the states of the data output pins(Q0-Q8). 

The M66850/851/852/853 have four flags (EF,FF,PAE,PAF). The empty flag EF and the full flag FF are fixed flags. The almost empty flag PAE and the almost full flag PAF are programmable flags. The programmable flag offset is initiated by the load pin(LD).