M65KG512AB

` 512Mbit Synchronous Dynamic RAM Organized as 4 banks of 8 Mwords, each 16 bits wide
` Double Data Rate (DDR) 2 Data Transfers/Clock cycle Data Rate: 332 Mbit/s max. for 6ns speed class
` Supply voltage VDD = 1.7 to 1.9 V (1.8 V typical in accordance with JEDEC standard) VDDQ = 1.7 to 1.9 V for Inputs/Outputs
` Synchronous Burst Read and Write Fixed Burst Lengths: 2-, 4-, 8-, 16 words Burst Types: Sequential and Interleaved. Clock Frequency: 133 MHz (7.5 ns speed class), 166 MHz (6 ns speed class) Clock Valid to Output Delay (CAS Latency): 3 at the maximum clock frequency Burst Read Control by Burst Read Terminate And Precharge Commands
` Automatic Precharge
` Byte Write controlled by LDQM and UDQM
` Low-power features Partial Array Self Refresh (PASR) Automatic Temperature Compensated Self Refresh (ATCSR) Driver Strength (DS) Deep Power-Down mode Auto Refresh and Self Refresh
` LVCMOS interface compatible with multiplexed addressing
` Operating temperature: −30 to 85 °C −30 to 105 °C

The M65KG512AB is a 512Mbit Double Data Rate (DDR) Low Power Synchronous DRAM (LPSDRAM). The memory array is organized as 4 Banks of 8,388,608 words of 16 bits each.

The device achieves low power consumption and very high-speed data transfer using the 2- bit prefetch pipeline architecture that allows doubling the data input/output rate. Command and address inputs are synchronized with the rising edge of the clock while data inputs/outputs are transferred on both edges of the system clock. The M65KG512AB is well suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and handheld computers.

M65KG512AB architecture is illustrated in Figure 2: Functional block diagram. It uses Burst mode to read and write data. It is capable of two, four, and eight-word, sequential and interleaved burst.