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M5M54R16AJ-12

Features: *Fast access time M5M54R16AJ,ATP-10 ... 10ns(max) M5M54R16AJ,ATP-12 ... 12ns(max) M5M54R16AJ,ATP-15 ... 15ns(max) *Single +3.3V power supply*Fully static operation : No clocks, No refresh*Common data I/O*Easy memory expansion byS*Three-state outputs : OR-tie capability*OE prevents data c...

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SeekIC No. : 004406314 Detail

M5M54R16AJ-12: Features: *Fast access time M5M54R16AJ,ATP-10 ... 10ns(max) M5M54R16AJ,ATP-12 ... 12ns(max) M5M54R16AJ,ATP-15 ... 15ns(max) *Single +3.3V power supply*Fully static operation : No clocks, No refresh*...

M5M54R16AJ-12 Data Sheet

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Part Number:
M5M54R16AJ-12
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

*Fast access time       M5M54R16AJ,ATP-10 ... 10ns(max)
                                   M5M54R16AJ,ATP-12 ... 12ns(max)
                                   M5M54R16AJ,ATP-15 ... 15ns(max)
                                        
*Single +3.3V power supply
*Fully static operation : No clocks, No refresh
*Common data I/O
*Easy memory expansion by S
*Three-state outputs : OR-tie capability
*OE prevents data contention in the I/O bus
*Directly TTL compatible : All inputs and outputs
*Separate control of lower and upper bytes by  LB and  UB 


Pinout

Connection Diagram


Specifications

Symbol Parameter Conditions Ratings Unit
Vcc Supply voltage With respect to GND - 2.0* ~ 4.6 V
VI Input voltage - 2.0* ~ Vcc+0.5 V
VO Output voltage
- 2.0* ~ Vcc		 V
Pd Power dissipation Ta=25 1000 mW
Topr Operating temperature   0 ~ 70  
Tstg(bias) Storage temperature(bias)   -10 ~ 85  
Tstg Storage temperature   -65 ~ 150  



Description

  The M5M54R16A is a family of 262144-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high  speed application. These devices operate on a single 3.3V supply, and are directly TTL  compatible.

  They  include  a  power down  feature as well.  In write and read cycles,  the  lower  and  upper  bytes  are  able  to  be controled  either  togethe  or  separately  by  LB and  UB.




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