Features: ` SUPPLY VOLTAGE
VDD = VDDQ = 1.65V to 2.0V for Program,Erase and Read
VPP = 12V for fast Program (optional)
` MULTIPLEXED ADDRESS/DATA
`SYNCHRONOUS / ASYNCHRONOUS READ
Configurable Burst mode Read
Page mode Read (4 Words Page)
Random Access: 100ns
` PROGRAMMING TIME
10s by Word typical
Double Word Programming Option
` MEMORY BLOCKS
Dual Bank Memory Array: 8 Mbit - 24 Mbit
Parameter Blocks (Top or Bottom location)
`DUAL BANK OPERATIONS
- Read within one Bank while Program or Erase within the other
No delay between Read and Write operations
` BLOCK PROTECTION/UNPROTECTION
All Blocks protected at Power-up
Any combination of Blocks can be protected
` COMMON FLASH INTERFACE (CFI)
` 64 bit SECURITY CODE
` ERASE SUSPEND and RESUME MODES
`100,000 PROGRAM/ERASE CYCLES per BLOCK
`ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Top Device Code, M59MR032C: A4h
Bottom Device Code, M59MR032D: A5hPinout
|
Symbol |
Quantity |
Value |
Unit |
|
TA |
Ambient Operating Temperature (2) |
-40to85 |
°C |
|
TBIAS |
Temperature Under Bias |
-40to125 |
°C |
|
TSTG |
Storage Temperature |
-55to155 |
°C |
|
VIO(3) |
Input or Output Voltage |
-0.5toVDDQ+0.5
|
V
|
|
VDD,VDDQ |
Supply Voltage |
-0.5to2.7 |
V |
|
VPP |
Program Voltage |
-0.5to13 |
V |
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Depends on range.
3. Minimum Voltage may undershoot to 2V during transition and for less than 20ns.
DescriptionThe M59MR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.0V VDD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally.The device supports synchronous burst read
and asynchronous page mode read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz.
The M59MR032 array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then reprotected.
Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume,Block Protect, Block Unprotect, Block Locking,CFI Query, are written to the memory through
a Command Interface (C.I.) using standard microprocessor write timings.
The M59MR032 memory is offered in LFBGA54 and BGA46,0.5 mm ball pitch packages and it is supplied with all the bits erased (set to '1').
M59MR032D Data Sheet
