M58PR512LE

The M58PR512LE and M58PR001LE are 512 Mbit (32 Mbit x 16) and 1 Gbit (64 Mbit x 16) non-volatile flash memories. They are collectively referred to as the M58PRxxxLE in the rest of the document, unless otherwise specified.

The M58PRxxxLE may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming.

The M58PRxxxLE has a uniform block architecture and is based on a multilevel cell technology:
The M58PR512LE has an array of 256 blocks, and is divided into 64 Mbit banks. There are 8 banks each containing 32 blocks of 128 KWords.
The M58PR001LE has an array of 512 blocks, and is divided into 128 Mbit banks.There are 8 banks each containing 64 blocks of 128 KWords.

Each block M58PR512LE and M58PR001LE contains 256 program regions of 1 Kbyte each, that are divided into 32 segments of 16 words. Each segment is split into two halves (A and B), according by the value on address input A3.The memory map is illustrated in Figure 4 and the main array architecture in Figure 5.

The M58PR512LE and M58PR001LE multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries.The bank architectures are summarized in Table 2 and Table 3, and the memory maps are shown in Figure 4 and .

Each block M58PR512LE and M58PR001LE can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming.

M58PR512LE and M58PR001LE Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards.

The device M58PR512LE and M58PR001LE supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 108 MHz.The device features an automatic standby mode and deep power-down mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven.

The M58PR512LE and M58PR001LE DPD (deep power-down) mode starts when the device is properly configured (ECR bit 15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power consumption.

The M58PRxxxLE features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up.

In addition to the main memory array, the M58PRxxxLE features an extended flash array (EFA) divided into 4 blocks of 64 Kbits each.

The EFA blocks M58PR512LE and M58PR001LE are accessed through a separate set of commands. The operations available in the EFA blocks are asynchronous read (in non-page mode), single word program, erase and block locking. See Section 4: Command interface for details of the EFA commands set.

See Table 4 for an extended flash array memory map. Table 18 and Table 19 describe the simultaneous operations allowed in the EFA blocks and the main memory array.The device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 OTP (one-time-programmable) protection registers of 128 bits each. The first protection register is divided into two areas: a 64-bit area containing a unique device number written by ST, and a 64-bit area one-time-programmable by the user. The user programmable area can be permanently protected. Figure 6, shows the Protection Register memory map.

The M58PR512LE and M58PR001LE memory is available in TFBGA105 or TFBGA107 packages, and is supplied with all the bits erased (set to '1')