M54HCT393

Features: HIGH SPEED fMAX = 80 MHz (TYP.) AT VCC = 5 VLOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °CHIGH NOISE IMMUNITY VIH = 2V (MIN.) VIL = 0.8V (MAX)OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL= 4 mA (MIN.) BALANCEDPROPAGATION DELAYS tPLH = tPHLPIN AND FUNCT...

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SeekIC No. : 004405986 Detail

M54HCT393: Features: HIGH SPEED fMAX = 80 MHz (TYP.) AT VCC = 5 VLOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °CHIGH NOISE IMMUNITY VIH = 2V (MIN.) VIL = 0.8V (MAX)OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYM...

floor Price/Ceiling Price

Part Number:
M54HCT393
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

HIGH SPEED fMAX = 80 MHz (TYP.) AT VCC = 5 V
LOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY VIH = 2V (MIN.) VIL = 0.8V (MAX)
OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL= 4 mA (MIN.)
BALANCEDPROPAGATION DELAYS tPLH = tPHL
PIN AND FUNCTION COMPATIBLE WITH 54/74LS393



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
Supply Voltage
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Source Sink Current Per Output Pin
± 25
mA
ICC or IGND
DC VCC or Ground Current
± 50
mA
PD
Power Dissipation
500 (*)
mW
Tstg
Storage Temperature
-65 to +150
°C
TL
Lead Temperature (10 sec)
300
°C
AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 derate to 300mWby 10mW/: 65 to85



Description

The M54/74HCT393 is a high speed CMOS DUAL BINARY COUNTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true COMS low power consumption.

This counter circuit M54/74HCT393 contains independent ripple carry counters and two 4-bit ripple carry binary counters, which can be cascated to create a single divide by 256 counter.

Each 4-bit counter M54/74HCT393 is incremented on the high to low transition (negative edge) of the clock input,and each has an independent clear input. When clear is set to high all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide by N counter configurations.

This integrated circuit M54/74HCT393 has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.

M54/74HCT393 All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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