Features: `HIGH SPEED`tPD = 11 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION`ICC = 1 A (MAX.) AT TA = 25 HIGH NOISE IMMUNITY`COMPATIBLE WITH TTL OUTPUTS`VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY`10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE`|IOH| = IOL = 4 mA (MIN.) BALANCEDPROPAGATION ...
M54HCT02: Features: `HIGH SPEED`tPD = 11 ns (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION`ICC = 1 A (MAX.) AT TA = 25 HIGH NOISE IMMUNITY`COMPATIBLE WITH TTL OUTPUTS`VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE C...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
±20 |
mA |
IOK |
DC Output Diode Current |
±20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
±25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
±50 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
|
TL |
Lead Temperature (10 sec) |
300 |
AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: @ 65 derate to 300mWby 10mW/: 65 to 85
The M54/74HCT02 is a high speed CMOS QUAD 2-INPUT NOR GATE fabricated in silicon gate C2MOStechnology. M54/74HCT02 has the same highspeed performance of LSTTL combined with true CMOS low power consumption. The internal circuit M54/74HCT02 is composed of 3 stages including buffer output, which gives high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
This integrated circuit hM54/74HCT02 as input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.