M54HC564

Features:

.HIGHSPEED fMAX =62 MHz(TYP.) ATV_CC =5V
.LOWPOWER DISSIPATION I_CC =4 A(MAX.)AT T_A =25°C
.HIGHNOISEIMMUNITY V_NIH =V_NIL = 28%V_CC (MIN)
.OUTPUTDRIVE CAPABILITY 15 LSTTLLOADS
.SYMMETRICALOUTPUTIMPEDANCE IOL =?IOH?=6 mA(MIN.)
.BALANCEDPROPAGATIONDELAYS tPLH =tPHL
.WIDE OPERATINGVOLTAGERANGE V_CC (OPR)= 2V TO6 V PIN ANDFUNCTION COMPATIBLE
.WITH 54/74LS564/574


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Source Sink Current Per Output Pin	± 35	mA
ICC or IGND	DC VCC or Ground Current	± 70	mA
PD	Power Dissipation	500 (*)	mW
Tstg	Storage Temperature	-65 to +150	OC
TL	Lead Temperature (10 sec)	300	OC

Description

The M54/74HC564andM54HC574 arehighspeed CMOSOCTALD-TYPEFLIPFLOPWITH3-STATE 2 OUTPUTS fabricated with in silicon gate C MOS technology. M54/74HC564andM54HC574 have the same high speed per- formanceof LSTTLcombined with true CMOSlow ower comsuption. These8-bit D-typeflip-flops are ontrolledbyaclockinput(CK)andanouputenable nput(OE).Onthepositivetransitionoftheclock,the outputswillbesettothelogicstatethatweresetup t the D inputs (HC574) or their omplement(HC564).

Whilethe M54/74HC564andM54HC574 OEinput is low,the eightoutputswillbe n anormal logic state(highor lowlogiclevel), and hilehigh level,theoutputs willbe inahigh pedancestate.Theoutputcontroldoes notaffectthein- ernaloperationofflip-flops.Thatis,theolddatacan e retained or the new data can be entered even hilethe outputs areoff. The application engineer asachoice ofcombinationofinverting andnon-in- erting outputs. The 3-state output configuration nd thewide oiceofoutline make bus-organized ystemssimple.Allinputs areequipped withprotection circuits against static discharge and transient xcessvoltage.