Features: HIGH SPEED tPD =13 ns (TYP.) AT VCC = 5VLOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C 6 VHIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSSYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCEDPROPAGATION DELAYS tPLH= tPHL WIDE OPERATIN...
M54HC195: Features: HIGH SPEED tPD =13 ns (TYP.) AT VCC = 5VLOWPOWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25 °C 6 VHIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSSYMM...
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Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature (10 sec) |
300 |
°C |
The M54/74HC195 is a high speed CMOS 4 BIT PIPO SHIFT REGISTER fabricated in silicon gate C2MOStechnology. It has the same highspeed performance of LSTTL combined with true CMOS low power consumption.
This shift register M54/74HC195 features parallel inputs, parallel outputs, J-K serial inputs, a SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in twomodes : Parallel Load ; Shift from QAtowards QD.
Parallel loading M54/74HC195 is accomplished by applying the four bits of data, and taking the SHIFT/LOAD control input low. The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the SHIFT/LOAD control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truthtable.
M54/74HC195 All inputs are equipped with protection circuits against static discharge transient excess voltage.