Features: HIGHSPEED fMAX =57 MHz(TYP.) ATVCC =5VLOWPOWER DISSIPATION ICC =4 A(MAX.)AT TA =25HIGHNOISEIMMUNITY VNIH =VNIL =28%VCC (MIN.)OUTPUTDRIVE CAPABILITY 10 LSTTLLOADSSYMMETRICALOUTPUTIMPEDANCE |IOH|=IOL =4 mA(MIN.)BALANCEDPROPAGATIONDELAYS tPLH =tPHLWIDE OPERATINGVOLTAGERANGE VCC (OPR)= 2V TO...
M54HC166: Features: HIGHSPEED fMAX =57 MHz(TYP.) ATVCC =5VLOWPOWER DISSIPATION ICC =4 A(MAX.)AT TA =25HIGHNOISEIMMUNITY VNIH =VNIL =28%VCC (MIN.)OUTPUTDRIVE CAPABILITY 10 LSTTLLOADSSYMMETRICALOUTPUTIMPEDANCE ...
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Symbol |
Parameter |
Value |
Unit |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VI |
DC Input Voltage |
-0.5 to VCC + 0.5 |
V |
VO |
DC Output Voltage |
-0.5 to VCC + 0.5 |
V |
IIK |
DC Input Diode Current |
± 20 |
mA |
IOK |
DC Output Diode Current |
± 20 |
mA |
IO |
DC Output Source Sink Current Per Output Pin |
± 25 |
mA |
ICC or IGND |
DC VCC or Ground Current |
± 50 |
mA |
PD |
Power Dissipation |
500 (*) |
mW |
Tstg
TL |
Storage Temperature
Lead Temperature (10 sec) |
-65 to +150
300 |
The M54/74HC166 is a high speed C2MOS 8 BITPISO SHIFT REGISTER fabricated in silicon gate C2MOStechnology.Ithasthesamehighspeedper-formance ofLSTTLcombined with trueCMOSlowpowerconsumption.
Itconsistsof parallel orserialinputsandaserial-out8-bit shift register with gated clock inputs and anoverriding clear input. The parallel-in or serial-inmodes are controlled by the SHIFT/LOAD input.WhentheSHIFT/LOAD inputisheldhigh, theserialdatainputisenabledandtheeightflipflopsperformserialshiftingwitheachclockpulse.Whenheldlow,theparalleldata inputs are enabled and syn-chronous loading occurs on the next clock pulse.Clocking is accomplished on the low-to-high leveledgeoftheclockpulse. TheCLOCK-INHIBITinputshould be changed to the high only while theCLOCKinput isheldhigh. Adirectclearinput over-rides all other inputs, including the clock, and setsallflip-flops tozero. Functional detailsareshowninthe truthtable andthe timing chart.
All inputs are equipped with protection circuitsagainst static discharge and transient excess volt-age.