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M54HC138

Features: HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 VLOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSBALANCEDPROPAGATION DELAYS tPLH = tPHLHIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 VPIN AND FUNCTION C...

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SeekIC No. : 004405818 Detail

M54HC138: Features: HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 VLOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADSBALANCEDPROPAGATION DELAYS tPLH = tPHLHIGH NOISE IMMUNITY...

M54HC138 Data Sheet

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Part Number:
M54HC138
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V
LOWPOWER DISSIPATION ICC = 4A (MAX.) AT TA = 25 °C
OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
BALANCEDPROPAGATION DELAYS tPLH = tPHL
HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) 
WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH 54/74LS138


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
 Supply Voltage
-0.5 to +7
V
VI
 DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
 DC Input Diode Current
± 20
mA
IOK
 DC Output Diode Current
± 20
mA
IO
 DC Output Source Sink Current Per Output Pin
± 25
mA
ICC or IGND
 DC VCC or Ground Current
± 50
mA
PD
 Power Dissipation
500 (*)
mW
Tstg
 Storage Temperature
-65 to +150
°C
TL
 Lead Temperature (10 sec)
300
°C
AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 derate to 300mWby 10mW/: 65 to85


Description

The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology.


The M54/74HC138 has the same high speed performance of LSTTL combined with true CMOS low power consumption. If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A orG2B is held high, the decoding function is inhibited and all the 8 outputs go high.

Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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