M54HC137

DECODER/LATCH (INVERTING) fabricated in silicon gate C²MOS technology. The M54HC137 has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC137 is a 3 to 8line decoder withlatches on thethree address inputs.When GL goes fromlowtohigh, theaddress present at theselect inputs (A, Band C) is stored in the latches. As long as GL remainshigh no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All the outputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped withprotection circuits against staticdischarge andtransient excess voltage.