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M54HC109

Features: HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION ICC = 2A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCEDPROPAGATION DELAYS tPLH = tPHL WIDE OPERAT...

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M54HC109: Features: HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V LOWPOWER DISSIPATION ICC = 2A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYM...

M54HC109 Data Sheet

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Part Number:
M54HC109
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

HIGH SPEED
    fMAX = 63 MHz (TYP.) AT VCC = 5 V
LOWPOWER DISSIPATION
   ICC = 2A (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY
    VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
   10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
  IOH = IOL = 4 mA (MIN.)
BALANCEDPROPAGATION DELAYS
    tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
   VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
   WITH 54/74LS109


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
 Supply Voltage
-0.5 to +7
V
VI
 DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
 DC Input Diode Current
± 20
mA
IOK
 DC Output Diode Current
± 20
mA
IO
 DC Output Source Sink Current Per Output Pin
± 25
mA
ICC or IGND
 DC VCC or Ground Current
± 50
mA
PD
 Power Dissipation
500 (*)
mW
Tstg
 Storage Temperature
-65 to +150
°C
TL
 Lead Temperature (10 sec)
300
°C
AbsoluteMaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 derate to 300mWby 10mW/: 65 to85


Description

The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology.

M54/74HC109 has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going transitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished bya low logic level on the corresponding input.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.




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