M50FW080

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK^® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Minimum voltage may undershoot to 2V for less than 20ns during transitions. Maximum voltage may overshoot to V_CC + 2V for less than 20ns during transitions.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )

The M50FW080 is an 8 Mbit (1Mbit x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times.

The memory M50FW080 is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end volatile memory that can be read, erased and reprogrammed.

These operations M50FW080 can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program  or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

Two different bus interfaces M50FW080 are supported by the memory. The primary interface, the Firmware Hub (or FWH) Interface, uses Intel's proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50FW080 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.

The secondary interface M50FW080, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard.