M48Z512A

` INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY
` CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES
`10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER
`AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION
`TWO WRITE PROTECT VOLTAGES: (V<sub>PFD</sub> = Power-fail Deselect Voltage)  M48Z512A: V<sub>CC</sub> = 4.75 to 5.5V 4.5V     V<sub>PFD</sub>     4.75V M48Z512AY: V<sub>CC</sub> = 4.5 to 5.5V 4.2V     V<sub>PFD</sub>    4.5V M48Z512AV: V<sub>CC</sub> = 3.0 to 3.6V 2.8V 3 V<sub>PFD</sub> 3 3.0V
` BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED
` PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 512K x 8 SRAMs
` SURFACE MOUNT CHIP SET PACKAGING (Figure 2) INCLUDES A 28-PIN SOIC and A 32- LEAD TSOP (SNAPHAT^® Top to be ordered separately)
` SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHATTOP WHICH CONTAINS THE BATTERY
` SNAPHAT HOUSING (BATTERY) IS REPLACEABLE

Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

With valid V_CC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDE^TM static RAM. Should the supply voltage decay, the RAM M48Z512A/Y/V will automatically power-fail deselect, write protecting itself t_WP after V_CC falls below V_PFD. All outputs become high impedance, and all inputs are treated as "don't care."

If power fail detection occurs of M48Z512A/Y/V during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time t_WP, write protection takes place. When V_CC drops below V_SO, the control circuit of M48Z512A/Y/V switches power to the internal energy source which preserves data.

The internal coin cell of M48Z512A/Y/V will maintain data in the M48Z512A/Y/V after the initial application of V_CC for an accumulated period of at least 10 years when V_CC is less than V_SO. As system power returns and V_CC rises above V_SO, the battery of M48Z512A/Y/V is disconnected, and the power supply is switched to external V_CC. Write protection continues for t_ER after V_CC reaches V_PFD to allow for processor stabilization. After t_ER, normal RAM operation can resume.

For more information about M48Z512A/Y/V on Battery Storage Life refer to the Application Note AN1012.