M48Z2M1Y

Features: INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERIES CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):...

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M48Z2M1Y Picture
SeekIC No. : 004405407 Detail

M48Z2M1Y: Features: INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERIES CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-...

floor Price/Ceiling Price

Part Number:
M48Z2M1Y
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/27

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Product Details

Description



Features:

INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERIES
CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION
WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):
    M48Z2M1: 4.5V VPFD 4.75V
    M48Z2M1Y: 4.2V VPFD 4.50V
BATTERIES ARE INTERNALLY ISOLATED UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 2Mb x 8 SRAMs



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
40 to 85
°C
TBIAS
Temperature Under Bias
40 to 85
°C
TSLD(2)
Lead Solder Temperature for 10 seconds
260
°C
VIO
Input or Output Voltages
0.3 to 7
V
VCC
Supply Voltage
0.3 to 7
V



Description

The M48Z2M1/2M1Y ZEROPOWER® RAM is a non-volatile 16,777,216 bit Static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36 pin DIP long Module.

The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed.




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