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M368L1624DTL

Features: • Performance range• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V• Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strobe(DQS)• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK t...

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SeekIC No. : 004404816 Detail

M368L1624DTL: Features: • Performance range• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V• Double-data-rate architecture; two data transfers per clock cycle• Bidirectional data strob...

M368L1624DTL Data Sheet

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Part Number:
M368L1624DTL
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component


Specifications

Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD

6
W
Short circuit current
IOS
50
mA

Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The Samsung M368L1624DTL is 16M bit x 64 Double Data Rate SDRAM high density memory modules.

The Samsung M368L1624DTL consists of four CMOS 16M x 16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOPII(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors M368L1624DTL are mounted on the printed circuit board in parallel for each DDR SDRAM.

The M368L1624DTL is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions M368L1624DTL are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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