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M34E02

Features: Software Data Protection for lower 128 bytes Two Wire I2C Serial Interface 100kHz Transfer Rates 1.7 to 3.6V Single Supply Voltage: BYTE and PAGE WRITE (up to 16 bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Pro...

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SeekIC No. : 004404773 Detail

M34E02: Features: Software Data Protection for lower 128 bytes Two Wire I2C Serial Interface 100kHz Transfer Rates 1.7 to 3.6V Single Supply Voltage: BYTE and PAGE WRITE (up to 16 bytes) RANDOM and SEQUENT...

M34E02 Data Sheet

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Part Number:
M34E02
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

Software Data Protection for lower 128 bytes
Two Wire I2C Serial Interface
100kHz Transfer Rates
1.7 to 3.6V Single Supply Voltage:
BYTE and PAGE WRITE (up to 16 bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention


Pinout

Connection Diagram


Specifications

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature -65 150 °C
TLEAD Lead Temperature during Soldering 1 See note 1 °C
VIO Input or Output range E0
Others		 -0.50
-0.50
 10.0
6.5		 V
VCC Supply Voltage -0.5 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 2 -4000 -4000 V
1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )


Description

The M34E02 is a 2 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM M34E02 module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory.

This bottom half of the memory area M34E02 can be writeprotected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resetable. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC).

These I2C-compatible electrically erasable programmable memory (EEPROM)M34E02 are organized as 256x8 bits.




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