M32000D4AFP

• CPU ..........................................................M32R family CPU core
• Pipeline ....................................................5 steps
• Basic bus cycle ....................................... 15 ns (at internal 66.6 MHz)
• Logical address space .............................4G-byte linear
• External bus ............................................data bus: 16 bits address bus: 24 bits
• Internal DRAM .........................................16M bits (2M bytes)
• Cache ......................................................4K bytes (direct map)
• Register configuration ............................ general-purpose registers: 32 bits x 16 control registers: 32 bits x 5
• Instruction set ....................................... 83 instructions/6 addressing modes
• Instruction format ...................................16 bits/32 bits
• Multiply-accumulate operation unit (DSP function instruction)
• Internal memory controller
• Programmable I/O ports
• Power management function ..................standby mode /CPU sleep mode
• PLL clock generating circuit .................... four-time clock PLL circuit
• Operation mode ..................................... master/slave mode
• Interrupt input ........................................INT and SBI
• Power source ..........................................3.3 V (±10 %)

The M32000D4AFP is a new generation microcomputer with a 32-bit CPU and built-in high capacity DRAM. Using this device it is possible to implement the complex applications of the multimedia age with high performance and low power consumption.

The M32000D4AFP contains 2M bytes of DRAM and 4K bytes of cache memory. The CPU is implemented with a RISC architecture and has a high performance figure of 52.4 MIPS (at an internal clock rate of 66.6 MHz ). Memory for main storage is provided internally to the device eliminating external memory and associated control circuits thus reducing overall system noise and power consumption.

The CPU, internal DRAM and cache memory are connected by a 128-bit, 15 ns/cycle internal bus which virtually eliminates transfer bottlenecks in between the CPU and the memory. The M32000D4AFP internally multiplies the frequency of the input clock signals by four.

For an internal operating frequency of 66.6 MHz the input clock frequency is 16.65MHz.

A 16-bit data and 24-bit address bus are the M32000D4AFP's external bus and the interface to external peripheral controllers. When the hold state is set, the internal DRAM can be accessed from an external device.

A 3-chip basic system configuration using the M32000D4AFP is the device itself plus an ASIC as a peripheral controller and a program ROM. Execution starts from the reset vector entry on the external ROM after power on, a program requiring high speed execution is then transferred to internal DRAM and this is then executed. The M32000D4AFP also has a slave mode additional to its master mode. When set to slave mode the M32000D4AFP can be used as a coprocessor. In this mode it does not access its external bus immediatly after reset, but waits for the master to start its operation.