M2V64S30BTP

Features: · Single 3.3v ± 0.3v power supply· Clock frequency 125MHz /100MHz· Fully synchronous operation referenced to clock rising edge· 4 bank operation controlled by BA0, BA1 (Bank Address)· /CAS latency- 2/3 (programmable)· Burst length- 1/2/4/8/Full Page (programmable)· Burst type- sequential...

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M2V64S30BTP Picture
SeekIC No. : 004404518 Detail

M2V64S30BTP: Features: · Single 3.3v ± 0.3v power supply· Clock frequency 125MHz /100MHz· Fully synchronous operation referenced to clock rising edge· 4 bank operation controlled by BA0, BA1 (Bank Address)· /CAS...

floor Price/Ceiling Price

Part Number:
M2V64S30BTP
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/27

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Product Details

Description



Features:

 · Single 3.3v ± 0.3v power supply
 · Clock frequency 125MHz /100MHz
 · Fully synchronous operation referenced to clock rising edge
 · 4 bank operation controlled by BA0, BA1 (Bank Address)
 · /CAS latency- 2/3 (programmable)
 · Burst length- 1/2/4/8/Full Page (programmable)
 · Burst type- sequential / interleave (programmable)
 · Column access - random
 · Burst Write / Single Write (programmable)
 · Auto precharge / All bank precharge controlled by A10
 · Auto refresh and Self refresh
 · 4096 refresh cycles /64ms
 · Column address A0-A9 (x4), A0-A8(x8), A0-A7(x16)
 · LVTTL Interface
 · 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch



Pinout

  Connection Diagram


Specifications



Symbol
Parameter
Conditions
Ratings
Unit
Vdd Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ Supply Voltage for Output
with respect to VssQ
-0.5 ~ 4.6
V
VI Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO Output Voltage
with respect to VssQ
-0.5~ VddQ+0.5
V
IO Output Current
50
mA
Pd Power Dissipation
Ta = 25
1000
mW
Topr Operating Temperature
0 ~ 70
Tstg Storage Temperature
-65 ~ 150





Description

The M2V64S30BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V64S20BTP, M2V64S30BTP, M2V64S40BTP achieve very high speed data rate up to 125MHz, and are suitable for main memory or graphic memory in computer systems.




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