Position: Home  > All Categories> Integrated Circuits (ICs) > M2S56D40ATP-75L

M2S56D40ATP-75L

Features: · VDD=VDDQ=2.5V+0.2V· Double data rate architecture; two data transfers per clock cycle· Bidirectional, data strobe (DQS) is transmitted/received with data· Differential clock inputs (CLK and /CLK)· DLL aligns DQ and DQS transitions· Commands are entered on each positive CLK edge· Data a...

product image

M2S56D40ATP-75L Picture
See larger image
SeekIC No. : 004404492 Detail

M2S56D40ATP-75L: Features: · VDD=VDDQ=2.5V+0.2V· Double data rate architecture; two data transfers per clock cycle· Bidirectional, data strobe (DQS) is transmitted/received with data· Differential clock inputs (CLK ...

M2S56D40ATP-75L Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
M2S56D40ATP-75L
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/27

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

 · VDD=VDDQ=2.5V+0.2V
 · Double data rate architecture; two data transfers per clock cycle
 · Bidirectional, data strobe (DQS) is transmitted/received with data
 · Differential clock inputs (CLK and /CLK)
 · DLL aligns DQ and DQS transitions
 · Commands are entered on each positive CLK edge
 · Data and data mask are referenced to both edges of DQS
 · 4-bank operations are controlled by BA0, BA1 (Bank Address)
 · /CAS latency- 2.0/2.5 (programmable)
 · Burst length- 2/4/8 (programmable)
 · Burst type- sequential / interleave (programmable)
 · Auto precharge / All bank precharge is controlled by A10
 · 8192 refresh cycles /64ms (4 banks concurrent refresh)
 · Auto refresh and Self refresh
 · Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
 · SSTL_2 Interface
 · Both 66-pin TSOP Package and 64-pin Small TSOP Package
     M2S56D*0ATP: 0.8mm lead pitch 66-pin TSOP Package
     M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package
 · JEDEC standard
 · Low Power for the Self Refresh Current ICC6 : 2mA (-75AL , -75L , -10L)


Specifications



Symbol
Parameter
Conditions
Ratings
Unit
VDD Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VDDQ Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI Input Voltage
with respect to Vss
-0.5 ~ VDD+0.5
V
VO Output Voltage
with respect to VssQ
-0.5~ VDDQ+0.5
V
IO Output Current
50
mA
Pd Power Dissipation
Ta = 25
1000
mW
Topr Operating Temperature
0 ~ 70
Tstg Storage Temperature
-65 ~ 150





Description

M2S56D40ATP-75L is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D40ATP-75L achieve very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Cables, Wires
821-0814-a
415-0100-150
Connectors, Interconnects
ASP-134488-01
WM4078-ND
Motors, Solenoids, Driver Boards/Modules
IHSS57-36-20
ASD-B2-1521-B
Power Supplies - Board Mount
HC-06
PM150RSA060-S81AH0G
Programmers, Development Systems
ARDUINO IIC/I2C 液晶模块
JTAG-SMT2
Isolators
HCPL062N
HCPL316J
View more