M24M01

Features: *400 kHz High Speed Two Wire I2C Serial Interface*Single Supply Voltage: 2.7V to 3.6V for M24M01-V 1.8V to 3.6V for M24M01-S*Write Control Input*BYTE and PAGE WRITE (up to 128 Bytes)*RANDOM and SEQUENTIAL READ Modes*Self-Timed Programming Cycle*Automatic Address Incrementing*Enhanced ESD...

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M24M01 Picture
SeekIC No. : 004404171 Detail

M24M01: Features: *400 kHz High Speed Two Wire I2C Serial Interface*Single Supply Voltage: 2.7V to 3.6V for M24M01-V 1.8V to 3.6V for M24M01-S*Write Control Input*BYTE and PAGE WRITE (up to 128 Bytes)*RANDO...

floor Price/Ceiling Price

Part Number:
M24M01
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

*400 kHz High Speed Two Wire I2C Serial Interface
*Single Supply Voltage:
2.7V to 3.6V for M24M01-V
1.8V to 3.6V for M24M01-S
*Write Control Input
*BYTE and PAGE WRITE (up to 128 Bytes)
*RANDOM and SEQUENTIAL READ Modes
*Self-Timed Programming Cycle
*Automatic Address Incrementing
*Enhanced ESD/Latch-Up Behavior
*More than 100000 Erase/Write Cycles
*More than 40 Year Data Retention

 




Specifications

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature 65 150   
TLEAD Lead Temperature during Soldering LGA: 20 seconds (max)1   235  
VIO Input or Output range 0.6 4.2  V
VCC Supply Voltage 0.3 4.2  V
VESD Electrostatic Discharge Voltage (Human Body model)2 3000 3000  V



Description

   The M24M01 is a 1 Mbit (131,072 x 8) electrically erasable programmable memory (EEPROM) ac-cessed by an I2 C-compatible bus.

    These devices M24M01 are compatible with the I2 C memo-ry protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2 C bus defini-tion.

   The M24M01 behaves as a slave in the I2 C protocol,with all memory operations synchronized by the serial clock. Read and Write operations are initiat-ed by a Start condition, generated by the bus mas-ter. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2),terminated by an acknowledge bit.




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