M24C64

These I²C-compatible electrically erasable programmablememory (EEPROM) devices are organizedas 8192 x 8 bits (M24C64) and 4096 x 8 bits(M24C32).

I²C uses a two-wire serial interface, comprising abi-directional data line and a clock line. The devicescarry a built-in 4-bit Device Type Identifier code(1010) in accordance with the I²C bus definition.The device behaves as a slave in the I²C protocol,with all memory operations synchronized by theserial clock. Read and Write operations are initiatedby a Start condition, generated by the bus master.The Start condition M24C64 is followed by a DeviceSelect Code and Read/Write bit (RW ) (as describedin Table 3.), terminated by an acknowledgebit.

When writing data to the memory, the M24C64 insertsan acknowledge bit during the 9th bit time,following the bus master's 8-bit transmission.When data is read by the bus master, the busmaster acknowledges the receipt of the data bytein the same way. Data transfers are terminated bya Stop condition after an Ack for Write, and after aNoAck for Read.