M2051

Integrated SAW delay line; Output of 15 to 700 MHz *
Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz)
Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios:
• M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
• M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
• M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin
Narrow Bandwidth control input (NBW Pin)
Hitless Switching (HS) options with or without Phase Build-out (PBO) available; performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The M2050/51/52 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.