M2004-01

Output Clock Frequency up to 700MHz
Differential LVPECL Outputs
Internal Low-jitter SAW-based Oscillator
Intrinsic Jitter <1ps rms (12kHz - 20MHz)
Jitter Attenuation of Input Reference Clock
Dual Input MUX
Parallel Programming
Tunable Loop Filter Response
Differential LVPECL Outputs
3.3V Operation
Small 9mm x 9mm SMT Package

Inputs, V_I: ....................................................-0.5 to V _CC+0.5V
Output, V_O: ...................................................-0.5 to V _CC +0.5V
Supply Voltage, V _DD :.........................................................4.6 V
Storage Temperature, T_STO :..............................-45 to +100

The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package.

The internal high "Q"± SAW filter provides low jitt signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz.

The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output frequency is an integer multiple of the input reference frequency.

Parallel and serial control of the output and feedback dividers M2004-01 is provided via the configuration logic. An external loop filter sets the PLL bandwidth
which can be optimized to provide jitter attenuation of the input reference clock.

The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz.