M13S128168A-5TG

M13S128168A-5TG is a type of double data rate sdram.

Features of the M13S128168A-5TG are:(1) JEDEC standard;(2) internal pipelined double-data-rate architecture, two data access per clock cycle;(3) bi-directional data strobe (DQS);(4) on-chip DLL;(5) differential clock inputs (CLK and CLK );(6) DLL aligns DQ and DQS transition with CLK transition;(7) quad bank operation;(8) CAS latency is 3;(9) burst length is 2, 4, 8.

The absolute maximum ratings of the M13S128168A-5TG can be summarized as:(1): voltage on any pin relative to VSS(VIN, VOUT) is -0.5 V to 3.6 V;(2): voltage on VDD supply relative to VSS(VDD,VDDQ) is -1.0 V to 3.6 V;(3): voltage on VDDQ supply relative to VSS(VDDQ) is -0.5 V to 3.6 V;(4): storage temperature(TSTG) is -55 to +150; (5): power dissipation(PD) is TBD W;(6): short circuit current(IOS) is 50 mA.