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LZ2523

Features: `Number of effective pixels : 512 (H) x 582 (V)`Number of optical black pixels- Horizontal : 2 front and 28 rear`Pixel pitch : 5.8 µm (H) x 3.8 µm (V)`Mg, G, Cy, and Ye complementary color filters`Low fixed-pattern noise and lag`No burn-in and no image distortion`Blooming sup...

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SeekIC No. : 004403783 Detail

LZ2523: Features: `Number of effective pixels : 512 (H) x 582 (V)`Number of optical black pixels- Horizontal : 2 front and 28 rear`Pixel pitch : 5.8 µm (H) x 3.8 µm (V)`Mg, G, Cy, and Ye complem...

LZ2523 Data Sheet

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Part Number:
LZ2523
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

`Number of effective pixels : 512 (H) x 582 (V)
`Number of optical black pixels
- Horizontal : 2 front and 28 rear
`Pixel pitch : 5.8 µm (H) x 3.8 µm (V)
`Mg, G, Cy, and Ye complementary color filters
`Low fixed-pattern noise and lag
`No burn-in and no image distortion
`Blooming suppression structure
`Built-in output amplifier
`Built-in overflow drain voltage circuit and reset gate voltage circuit
`Horizontal shift register clock voltage : 3.6 V (TYP.)
`Variable electronic shutter (1/50 to 1/10 000 s)
`Compatible with PAL standard
`Package : 14-pin half-pitch WDIP [Plastic] (WDIP014-P-0400A) Row space : 10.16 mm


Pinout

Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
NOTE
Output transistor drain voltage
VOD
0 to +18
V
Overflow drain voltage
VOFD

Internal output
V
1
Reset gate clock voltage
VRS
Internal output
V
2
Vertical shift register clock voltage
VV

-11.5 to +17.5
V
Horizontal shift register clock voltage
VH
-0.3 to +12
V
Voltage difference between P-well and vertical clock
VPW-VV
-29 to 0
V
Voltage difference between vertical clocks

VV-VV
0 to +15
V
3
Storage temperature
TSTG
-40 to +85
Ambient operating temperature
TOPR
-20 to +70


NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 27 Vp-p.
2. Do not connect to DC voltage directly. When RS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 V.




Description

The LZ2523 is a 1/5-type (3.6 mm) solid-state  image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices). With approximately 320 000 pixels (542 horizontal x 582 vertical), the sensor provides a stable high-resolution color image.




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