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LZ24BP

Features: ` Progressive scan` Square pixel` Compatible with VGA format` Number of effective pixels : 659 (H) x 494 (V)` Number of optical black pixels - Horizontal : 2 front and 31 rear - Vertical : 8 front and 2 rear` Number of dummy bits - Horizontal : 16 - Vertical : 5` Pixel pitch : 5.6 µ...

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SeekIC No. : 004403781 Detail

LZ24BP: Features: ` Progressive scan` Square pixel` Compatible with VGA format` Number of effective pixels : 659 (H) x 494 (V)` Number of optical black pixels - Horizontal : 2 front and 31 rear - Vertical :...

LZ24BP Data Sheet

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Part Number:
LZ24BP
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

` Progressive scan
` Square pixel
` Compatible with VGA format
` Number of effective pixels : 659 (H) x 494 (V)
` Number of optical black pixels
    - Horizontal : 2 front and 31 rear
    - Vertical : 8 front and 2 rear
` Number of dummy bits
   - Horizontal : 16
   - Vertical : 5
` Pixel pitch : 5.6 µm (H) x 5.6 µm (V)
` R, G, and B primary color mosaic filters
` Low fixed-pattern noise and lag
` No burn-in and no image distortion
` Blooming suppression structure
` Built-in output amplifier
` Built-in overflow drain voltage circuit and reset gate voltage circuit
` Horizontal shift register clock and reset gate clock voltage : 3.3 V (TYP.)
` Variable electronic shutter (1/30 to 1/10 000 s)
` Package : 14-pin half-pitch WDIP [Plastic] (WDIP014-P-0400A) Row space : 10.16 mm


Pinout

Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
NOTE
Output transistor drain voltage
VOD
0 to +18
V
Overflow drain voltage
VOFD

Internal output
V
1
Reset gate clock voltage
VRS
Internal output
V
2
Vertical shift register clock voltage
VV

-11.5 to +17.5
V
Horizontal shift register clock voltage
VH
-0.3 to +12
V
Voltage difference between P-well and vertical clock
VPW-VV
-29 to 0
V
Voltage difference between vertical clocks

VV-VV
0 to +15
V
3
Storage temperature
TSTG
-40 to +85
Ambient operating temperature
TOPR
-20 to +70


NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 27 Vp-p.
2. Do not connect to DC voltage directly. When RS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 V.




Description

The LZ24BP is a 1/4-type (4.5 mm) solid-state image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices). With approximately 350 000 pixels (692 horizontal x 504 vertical), the sensor provides a stable highresolution color image. All pixel signals can be read independently via the vertical shift register and horizontal shift register.




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