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LZ2423H

Features: ` Number of effective pixels : 512 (H) x 582 (V)` Number of optical black pixels -Horizontal : 2 front and 28 rear` Pixel pitch : 7.2 µm (H) x 4.7 µm (V)` Mg, G, Cy, and Ye complementary color filters` Low fixed-pattern noise and lag` No burn-in and no image distortion` Bloom...

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SeekIC No. : 004403777 Detail

LZ2423H: Features: ` Number of effective pixels : 512 (H) x 582 (V)` Number of optical black pixels -Horizontal : 2 front and 28 rear` Pixel pitch : 7.2 µm (H) x 4.7 µm (V)` Mg, G, Cy, and Ye com...

LZ2423H Data Sheet

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Part Number:
LZ2423H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

 ` Number of effective pixels : 512 (H) x 582 (V)
 ` Number of optical black pixels
     -Horizontal : 2 front and 28 rear
 ` Pixel pitch : 7.2 µm (H) x 4.7 µm (V)
 ` Mg, G, Cy, and Ye complementary color filters
 ` Low fixed-pattern noise and lag
 ` No burn-in and no image distortion
 ` Blooming suppression structure
 ` Built-in output amplifier
 ` Built-in overflow drain voltage circuit and reset gate voltage circuit
 ` Horizontal shift register clock and reset gate clock voltage : 3.3 V (TYP.)
 ` Variable electronic shutter (1/50 to 1/10 000 s)
 ` Compatible with PAL standard
 ` Package : 14-pin half-pitch WDIP [Plastic] (WDIP014-P-0400A) Row space : 10.16 mm


Pinout

Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
NOTE
Output transistor drain voltage
VOD
0 to +15
V
Overflow drain voltage
VOFD
Internal output
V
1
Reset gate clock voltage
VRS
Internal output
V
2
Vertical shift register clock voltage
VV
VPW to +15
V
Horizontal shift register clock voltage
VH
-0.3 to +12
V
Voltage difference between P-well and vertical clock
VPW-VV
-24 to 0
V
Voltage difference between vertical clocks
VV-VV
0 to +15
V
3
Storage temperature
TSTG
-40 to +85
Ambient operating temperature
TOPR
-20 to +70

NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 26 Vp-p.
2. Do not connect to DC voltage directly. When RS is connected to GND, connect VOD to GND. Reset gate clock s applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks ill be below 27 V.


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