LZ23J3V

Features: • Optical size : 6.72 mm (aspect ratio 4 : 3)• Interline scan format• Square pixel• Number of effective pixels : 1 292 (H) x 966 (V)• Number of optical black pixels Horizontal : 3 front and 49 rear Vertical : 3 front and 2 rear• Number of dummy bits ...

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LZ23J3V Picture
SeekIC No. : 004403774 Detail

LZ23J3V: Features: • Optical size : 6.72 mm (aspect ratio 4 : 3)• Interline scan format• Square pixel• Number of effective pixels : 1 292 (H) x 966 (V)• Number of optical black ...

floor Price/Ceiling Price

Part Number:
LZ23J3V
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/5

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Product Details

Description



Features:

• Optical size : 6.72 mm (aspect ratio 4 : 3)
• Interline scan format
• Square pixel
• Number of effective pixels : 1 292 (H) x 966 (V)
• Number of optical black pixels
  Horizontal : 3 front and 49 rear
  Vertical : 3 front and 2 rear
• Number of dummy bits
  Horizontal : 28
  Vertical : 2
• Pixel pitch : 4.2 µm (H) x 4.2 µm (V)
• R, G, and B primary color mosaic filters
• Supports monitoring mode
• Low fixed-pattern noise and lag
• No burn-in and no image distortion
• Blooming suppression structure
• Built-in output amplifier
• Built-in overflow drain voltage circuit and reset gate voltage circuit
• Variable electronic shutter
• Package : 16-pin shrink-pitch WDIP [Plastic] (WDIP016-P-0500C) Row space : 12.70 mm



Pinout

  Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
NOTE
Output transistor drain voltage
VOD
0 to +18
V
Overflow drain voltage
VOFD
Internal output
V
1
Reset gate clock voltage
VØRS
Internal output
V
2
Vertical shift register clock voltage
VØV
VPW to +18
V
Horizontal shift register clock voltage
VØH
0.3 to +12
V
Voltage difference between P-well and vertical clock
VPW-VØV
29 to 0
V
Voltage difference between vertical clocks
VØV-VØV
0 to +17
V
3
Storage temperature
TSTG
40 to +85
Ambient operating temperature
TOPR
20 to +70

NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock
    is applied below 33 Vp-p.
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock
    is applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical
    clocks  will be below 28 V.


Description

The LZ23J3V is a 1/2.7-type (6.72 mm) solid-state image sensor that consists of PN photo-diodes and CCDs (charge-coupled devices). With approximately 1 310 000 pixels (1 344 horizontal x 971 vertical), the sensor provides a stable highresolution color image.




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