LXT6234

· Performs four-E1 to one-E2, or four-E2 to one-E3 multiplexing. Five ICs will implement a sixteen-E1 to one-E3 multiplexer.
·Fully compliant with the G.742 and G.751 ITU recommendations. Fully compliant with G.703 when used with LXT305/332 Line Interface.
· A robust frame-acquisition and frameholding algorithm minimizes frame slippage, acquires and holds frame below 10^-2 bit error rate.
· Four auxiliary low speed data or flag channels are available via the Stuffing Bits on each tributary channel.
·Access to the Alarm bit and the National bit. These can be used as recommended by ITU or for proprietary use.
· Five independent HDB3 CODECs allow multiplexer I/O in either HDB3 or NRZ formats. The LXT6234 can also function as a stand alone five-channel HDB3 transcoder.

The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. All of the necessary circuitry is integrated into the LXT 6234 ERate Multiplexer; there is no need for an external framing device.

The LXT6234 E-Rate Multiplexer conforms to both the (ITU) G.742 and (ITU) G.751 multiplexing formats defined by the International Telecommunications Union (ITU; formerly known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame.

The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the multiplexer. The LXT6234 E-Rate Multiplexer can also serve as a five channel HDB3 coder and decoder.