Features: Up to Three Independently Regulated Outputs DDR Termination Compliant Bi-phase Current SharingOutputs As Low As 0.8V Generated From An Internal 1% Reference Multiphase High Current Output Reduces Required Capacitance Integrated High Current MOSFET Drivers 300KHz, 500KHz and 600KHz High ...
LX1672: Features: Up to Three Independently Regulated Outputs DDR Termination Compliant Bi-phase Current SharingOutputs As Low As 0.8V Generated From An Internal 1% Reference Multiphase High Current Output...
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Supply Voltage (VCC) DC.................................................................-0.3V to 5.5V
Supply Voltage (VCC) Transient ......................................................-0.3V to 6.0V
Driver Supply Voltage (VCx, VCCL) DC ............................................-0.3V to 16V
Driver Supply Voltage (VCx, VCCL) Transient ..................................-0.3V to 18V
Current Sense Inputs (VSX, CSX) ....................................................... -0.3V to 12V
Error Amplifier Inputs (FBX, RF2)....................................................-0.3V to 5.5V
Input Voltage (SS/SHDN) ..................................................................-0.3V to5.5V
Output Drive Peak Current Source (HOx, LOx)....................................1A (500ns)
Output Drive Peak Current Sink (HOx, LOx) .......................................1A (500ns)
Operating Junction Temperature.................................................................. 150°C
Storage Temperature Range...........................................................-65°C to 150°C
RoHS Peak Package Solder Reflow Temperature
(40 second maximum exposure) ..................................................... 260°C (+0, -5)
The LX1672 is a highly integrated power supply controller IC featuring two PWM switching regulator stages with an additional onboard linear regulator driver. The two constant frequency voltagemode PWM phases can be easily configured as a single Bi-Phase high current output, two independently regulated outputs, or as a DDR memory I/O supply with a tracking DDR termination voltage supply. Power loss and noise, due to the ESR of the input capacitors, are minimized by operating each PWM output 180° out of phase. This architecture also minimizes capacitor requirements while maximizing regulator response.