Features: • Fastest 3V PLD• Supports 3/5V mixed systems• Low ground bounce (<1.1V worst case)• Live insertion/extraction permitted• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs• Metastable hardened device•...
LVT22V10: Features: • Fastest 3V PLD• Supports 3/5V mixed systems• Low ground bounce (<1.1V worst case)• Live insertion/extraction permitted• Bus-hold data inputs eliminate th...
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Parameter |
Symbol |
RATINGS
|
Units | |
Min | Max. | |||
Supply voltage2 |
VCC |
0.5 |
+4.6 |
VDC |
Input voltage2 |
VIN |
0.5 |
7 |
VDC |
Output voltage3 |
VOUT |
0.5 |
5.5 |
VDC |
Input currents |
IIN |
30 |
+30 |
mA |
Output currents |
IOUT |
+100 |
mA | |
Storage temperature range |
Tstg |
65 |
+150 |
°C |
The LVT22V10 is a versatile PAL) device fabricated on the Philips BiCMOS QUBiC process.
The LVT22V10 QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V.
The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V.
The LVT22V10 designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly, or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a
bus-hold data structure designed into the LVT input.
The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs.
The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is
specially designed so that during VCC ramp, the output remains 3-Stated until VCC 2.1V. At that time the outputs become fully functional depending upon device inputs. (See DC Electrical Characteristics, Symbol IPU/PD, Page 5). In addition when an LVT 22V10 output is tied to a 5V bus, no bus current is loaded.The LVT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations.
This device LVT22V10 has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.