LTC2230

Features:

Sample Rate: 170Msps/135 Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 890mW/660mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
    170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
    135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm x 9mmQFN Package


Application

Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communicotion Test Equipmrnt


Pinout




Specifications

Supply Voltage (VDD).................................................4V
Digital Output Ground Voltage (OGND).......0.3V to 1V
Analog Input Voltage (Note 3).....0.3V to (VDD+ 0.3V)
Digital Input Voltage....................0.3V to (VDD+ 0.3V)
Digital Output Voltage...............0.3V to (OVDD+ 0.3V)
Power Dissipation............................................1500mW
Operating Temperature Range
LTC2230C, LTC2231C.................................0⁰C to 70⁰C
LTC2230I,  LTC2231I...............................-40⁰C to 85⁰C
Storage Temperature Range.................-65⁰C to 125⁰C




Description

The LTC^®2230 and LTC2231 are 170Msps/135Msps, sam-pling 10-bit A/D converters designed for digitizing highfrequency, wide dynamic range signals. The LTC2230/LTC2231 are perfect for demanding communicationsapplications with AC performance that includes 61dB SNRand 75dB spurious free dynamic range for signalsup to 200MHz. Ultralow jitter of 0.15psRMS allowsundersampling of IF frequencies with excellent noiseperformance.

DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)and no missing codes over temperature. The transitionnoise is a low 0.12LSBRMS.

The digital outputs of  LTC2230/LTC2231  can be either differential LVDS, orsingle-ended CMOS. There are three format options forthe CMOS outputs: a single bus running at the full data rateor two demultiplexed buses running at half data rate witheither interleaved or simultaneous update. A separateoutput power supply allows theCMOS output swing torange from 0.5V to 3.3V.

The ENC+ and ENC inputs may be driven differentially orsingle ended with a sine wave, PECL, LVDS, TTL, or CMOSinputs. An optional clock duty cycle stabilizer allows highperformance at full speed for a wide range of clock dutycycles.