Features: 32-bit Input, 32-bit Output Multiplexed to 16 Lines
Full 0-31 Position Barrel Shift Capability
Integral Priority Encoder for 32-bit Floating Point Normalization
Sign-Magnitude or Two's Complement Mantissa Representation
32-bit Linear Shifts with Sign or Zero Fill
Independent Priority Encoder Outputs for Block Floating Point
68-pin PLCC, J-Lead
ApplicationNormalization of mantissas up to 32 bits can be accomplished directly by a single LSH33. To do this, the NORM input is asserted, and fill mode and left shift are selected. The normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the MS/LS signal. If it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two LSH33 devices can be used in parallel. Both devices receive the same input word, with the MS/LS
select line of one wired high, and the other low. Each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously.
PinoutSpecificationsStorage temperature .............................................................65°C to +150°C Operating ambient temperature .................................................. 55°C to +125°C VCC supply voltage with respect toground ................................... 0.5 V to +7.0 V Input signal with respect to ground ...................................................3.0 V to +7.0 V Signal applied to high impedance output ................................ 3.0 V to +7.0 VOutput current into ow outputs .................................................................25 mAL atchup current ...........................................................................................> 400 mA
DescriptionThe LSH33 is a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. LSH33 has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, including circular (barrel) shifting, left shifts with zero fill, and right shifts with sign extension are possible. In addition, a built-in priority encoder is provided to aid floating point normalization.
Input/Output registers provide complete pipelined operation. Both have independent bypass paths for complete flexibility. When FTI = 1, the input registers are bypassed. Likewise, when FTO= 1, the output registers are bypassed.