LPC2101

16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.
2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms.
EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software.
The 10-bit A/D converter provides eight analog inputs, with conversion times as low as 2.44 ms per channel and dedicated result registers to minimize interrupt overhead.
Two 32-bit timers/external event counters with combined seven capture and seven compare channels.
Two 16-bit timers/external event counters with combined three capture and seven compare channels.
Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input.
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with uffering and variable data length capabilities.
Vectored interrupt controller with configurable priorities and vector addresses.
Up to thirty-two 5 V tolerant fast general purpose I/O pins.
Up to 13 edge or level sensitive external interrupt pins available.
70 MHz maximum CPU clock available from programmable on-chip PLL with a possible input frequency of 10 MHz to 25 MHz and a settling time of 100 ms.
On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz.
Power saving modes include Idle mode, Power-down mode with RTC active, and Power-down mode.
Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power ptimization.
Processor wake-up from Power-down mode via external interrupt or RTC.

The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for applications where miniaturization is a key requirement. A blend of serial communications interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication gateways and protocol converters. The superior performance also makes these devices suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.