LP61L256B

Features:

· Single +3.3 volt power supply
· Access times: 12 ns (max.)
· Current: Operating: 100mA (max.) Standby: 10mA (max.)
· Full static operation, no clock or refreshing required
· All inputs and outputs directly TTL compatible
· Common I/O using three-state output
· Data retention voltage: 2V (min.)
· Available in 28-pin SOJ and TSOP packages


Pinout




Specifications

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . . .  -0.3V to VCC +0.3V
Operating Temperature, Topr . . . . . . . . . . . 0 to +70
Storage Temperature, Tstg . . . . . . . . . . -55 to +125
Power Dissipation, Pt . . . . . . . . . . . . . . . . . . . . . . . 1.0W


Description

·The LP61L256B is a high-speed, low-power 262,144-bit static random access memory organized as 32,768 words by 8 bits that operates on a single 3.3V power supply.

·Input and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

·Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels.

·Data retention is guaranteed at a power supply voltage as low as 2V.